The present invention relates to a polyphase clock generation circuit which employs a clock driver of the Complementary Metal Oxide Semiconductor (CMOS) inverter configuration.
In recent years, there has been a progressively increasing demand for high-speed operation and low-power dissipation in semiconductor integrated circuits for use in microcomputers or like electronic apparatus in which desired processing is executed in response to polyphase clocks. However, the characteristics of actual semiconductor integrated circuits cannot satisfy this demand because the power dissipation of these circuits increases as the speed of operation increases. As a conventional example of polyphase clock generation circuit used to generate polyphase clocks in such semiconductor integrated circuits, a two-phase clock generation circuit which generates from a single-phase clock .phi. a first clock .phi..sub.1 and a second clock .phi..sub.2 of different phase is described below with reference to FIG. 1.
The two-phase clock generation circuit 100 includes an inverter 101, a first NAND gate 102, a second NAND gate 103, a first delay circuit 104, a second delay circuit 105, a first clock driver 106, and a second clock driver 107. The inverter 101 inverts the polarity of the single-phase clock .phi. to produce an inverted clock .phi.'. The first NAND gate 102 negates the logical AND between the single-phase clock .phi. and the output signal of the second delay circuit 105. The second NAND gate 103 negates the logical AND between the inverted clock .phi.' and the output signal of the first delay circuit 104. The first delay circuit 104 delays the output signal of the first NAND gate 102 by a predetermined first delay time dt.sub.1. The second delay circuit 105 delays the output signal of the second NAND gate 103 by a predetermined second delay time dt.sub.2. The first clock driver 106 has the configuration of a CMOS inverter formed from a first PMOS transistor M.sub.p1 and a first NMOS transistor M.sub.n1, and inverts the polarity of the output signal of the first NAND gate 102 to produce the first clock .phi..sub.1. The second driver 107 has the configuration of a CMOS inverter formed from a second PMOS transistor M.sub.p2 and a second NMOS transistor M.sub.n2, and inverts the polarity of the output signal of the second NAND gate 103 to produce the second clock .phi..sub.2.
The operation of the two-phase clock generation circuit 100 is described with reference to a timing chart shown in FIG. 2. It is assumed that, as an initial state, sufficient time has passed while the single-phase clock .phi. remains at high level and the two-phase clock generation circuit 100 is in a stable condition. In this condition, the first clock .phi..sub.1 is at high level while the second clock .phi..sub.2 is at low level, as shown at time t.sub.0 in FIG. 2. When the single-phase clock .phi. subsequently changes to low level at time t.sub.1, the output signal of the first NAND gate 102 changes to high level, and consequently, the first clock .phi..sub.1 changes from high level to low level after the delay of the delay time provided by the first clock driver 106. Meanwhile, at time t.sub.1, the inverted clock .phi.' outputted from the inverter 101 changes to high level. However, since the output signal of the first NAND gate 102 is inputted to the second NAND gate 103 only after the delay of the delay time dt.sub.1 of the first delay circuit 104, the output signal of the first NAND gate 102 changes from high level to low level after the delay of the first delay time dt.sub.1 from time t.sub.1. As the delay time at the second clock driver 107 is substantially equal to the delay time at the first clock driver 106, the second clock .phi..sub.2 changes from low level to high level after the delay of the first delay time dt.sub.1 that commences when the first clock .phi..sub.1 changes from high level to low level. Thereafter, when the single-phase clock .phi. changes from low level to high level at time t.sub.2, the inverted clock .phi.' outputted from the inverter 101 changes to low level. As a result, the output signal of the second NAND gate 103 changes to high level and the second clock .phi..sub.2 changes from high level to low level after the delay of the delay time at the second clock driver 107. Meanwhile, at time t.sub.2, the output signal of the second NAND gate 103 changes to high level. However, since the output signal of the second NAND gate 103 is inputted to the first NAND gate 102 after the delay of the second delay time dt.sub.2 of the second delay circuit 105, the output signal of the first NAND gate 102 changes from high level to low level after the delay of the second delay time dt.sub.2 from the time t.sub.2. As the delay time at the first clock driver 106 is substantially equal to the delay time at the second clock driver 107, the first clock .phi..sub.1 changes from low level to high level after the delay of the second delay time dt.sub.2 that commences when the second clock .phi..sub.2 changes from high level to low level. Thereafter, the operations described above take place repetitively. Accordingly, in the two-phase clock generation circuit 100, the first and second clocks .phi..sub.1 and .phi..sub.2 do not exhibit an overlapping condition of high level thereof and repeat their level variations in synchronism with the single-phase clock .phi..
In a semiconductor integrated circuit in which processing is executed in response to polyphase clocks, it is normally necessary that active periods (periods of high level or low level) of the clocks do not overlap with each other. This is because cases in which the active periods of the clocks overlap with each other can cause malfunction of the semiconductor integrated circuit such as a direct transmission phenomenon of data in a latch of the master-slave configuration. Accordingly, a polyphase clock generation circuit must generate clocks such that the magnitude of the displacement between the timing of a level variation of one clock and the timing of a level variation of another clock (that is, a delay between the clocks) may be greater than the magnitude of the gradient of the waveform of the rising or falling edge of the one clock. However, the magnitude of the gradient of the waveform of the rising or falling edge of the clock depends upon the power source voltage for driving the polyphase clock generation circuit (that is, an application of the polyphase clock generation circuit), the weight of the lead to the polyphase clock generation circuit, and various other parameters. For example, the gradient of the waveform of the rising or falling edge of the clock when the polyphase clock generation circuit is used with a system wherein the power source voltage is 3 V is higher than that when the polyphase clock generation circuit is used with another system wherein the power source voltage is 5 V, and accordingly, the delay between the clocks must be greater where the power source voltage is 3 V. However, although increasing the delay between clocks increases the margin of safety against malfunctions, increased delay also decreases the operation speed of the semiconductor integrated circuit which operates with the clocks. Accordingly, as the delay between clocks has an appropriate magnitude suitable for the application, a polyphase clock generation circuit is preferably constructed so as to allow adjustment of the delay between clocks from the outside in order to increase the applicability of the polyphase clock generation circuit to various applications.
Since the first clock driver 106 shown in FIG. 1 is constructed from the inverter of the CMOS configuration formed from the first PMOS transistor M.sub.p1 and the first NMOS transistor M.sub.n1, it has input/output characteristic such as the characteristics illustrated in FIG. 3. When the input voltage V.sub.IN to the first clock driver 106 (that is, the voltage of the output signal of the first NAND gate 102) is substantially equal to 0 V, the first PMOS transistor M.sub.p1 is ON and the first NMOS transistor M.sub.n1 is OFF, and consequently, the output voltage V.sub.OUT of the first clock driver 106 (that is, the voltage of the first clock .phi..sub.1) is substantially equal to the power source voltage V.sub.DD. On the other hand, when the input voltage V.sub.IN is substantially equal to the power source voltage V.sub.DD, the first PMOS transistor M.sub.p1 is OFF and the first NMOS transistor M.sub.n1 is ON, and consequently, the output voltage V.sub.OUT is substantially equal to 0 V. Accordingly, within a period within which the first clock driver 106 is in a stable condition, such as a period "a" or another period "c" shown in FIG. 3, at least one of the first PMOS transistor M.sub.p1 and the first NMOS transistor M.sub.n1 is OFF, and no through-current flows through the first clock driver 106. As a result, the power dissipation of the first clock driver 106 in a stable condition is very low. However, within a period of a transition condition such as a period "b" shown in FIG. 3, the first PMOS transistor M.sub.p1 and the first NMOS transistor M.sub.n1 are both ON, and through-current flows through the first clock driver 106. The through-current increases as the channel widths (that is, the conductance) of the first PMOS transistor M.sub.p1 and the first NMOS transistor M.sub.n1 increase and as the operation frequency (that is, the frequency of the single-phase clock .phi.) increases.
Accordingly, conventional polyphase clock generation circuits which include clock drivers of the CMOS inverter configuration such as the two-phase clock generation circuit 100 shown in FIG. 1 have problems in that the power dissipation is high since through-current flows upon switching of the clock drivers, that the power dissipation by the clock drivers increases as the operation frequency increases, and that power source noise or ground noise is produced.